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Parallel Computing Technologies Third International Conference (PaCT-95) September 12-15, 1995. St.-Petersburg, Russia Proceedings Home PaCTs Prev Contents Next Authors
	Vol. 964

DFS-SuperMPx: Low-cost Parallel Processing System for Machine Vision and Image Processing

by V. P. Srini

Abstract:
The architecture of a low-cost hosted MIMD parallel processing system containing parallel processor chips interconnected by a hierarchy of crossbars is described. The parallel processing system is attached to the system bus of the host and uses the operating system and programming environment of the host. Each parallel processor chip contains 64 processors. The processors in a chip are simple in their architecture and structured so that data streams can be processed efficiently using datafiow semantics. A static datafiow model of computation is assumed for programming the chip. Arithmetic, logical, multiply, conditional branch, and select instructions are supported. Each processor has a 16-bit data path and a microcontroller. The processors in a chip are clustered for reducing data communication latency time. Eight processors are grouped into a cluster and there are eight clusters in a chip. Segmented and switched buses are used for intra and inter cluster communication in a chip. A global bus is provided for supplying instructions to the processors during program setup and to communicate the status of the processors during program execution. Two global buses are provided for data transfer between the external memory or I/O devices and the data memories of the processors. Each chip has two ports with 16 bits of data, 16 bits for processor address, and control signals for connecting to other chips using a hierarchical crossbar interconnection network. The interconnection network is based on a 16 X 16 crossbar chip with 32 ports (16 paths) capable of connecting 16 processor chips or 15 processor chips and a second level of crossbar chip. With two levels of crossbar chips it is possible to connect 225 parallel processor chips and achieve one Teraop in a shoebox sized system. The applications selected for the parallel processing system are image processing, machine vision, video compression and decompression, and 3-D imaging.

Keywords: Hardware and Architecture



Classification:
	C.1	processor architectures
	C.2	computer-communication networks
	C.3	special-purpose and application-based systems; microprocessor/microcomputer applications; process control systems; real-time systems; signal processing systems
	C.4	performance of systems; design studies; measurement techniques; modeling techniques; performance attributes; reliability, availability, and serviceability
	D.1	programming techniques
	D.2	software engineering
	D.3	programming languages
	D.4	operating systems
	F.1	computation by abstract devices
	F.2	analysis of algorithms and problem complexity


Source:
V. P. Srini, DFS-SuperMPx: Low-cost Parallel Processing System for Machine Vision and Image Processing.
In V. Malyshkin (ed.), Parallel Computing Technologies: Proceedings of the 3th International Conference, Lect. Notes in Comp. Sci., Vol. 964, Springer, 1995, pp. 356-369

ISSN 0302-9743
ISBN 3-540-60222-4

Search LNCS articles for:
Srini, V. P.



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