Hosted with the Supercomputer Software Department RAS Home
Parallel Computing Technologies Third International Conference (PaCT-95) September 12-15, 1995. St.-Petersburg, Russia Proceedings Home PaCTs Prev Contents Next Authors
	Vol. 964

Design and Evaluation of a Multi-Threaded Architecture for Parallel Graph Reduction

by F. Caudal, B. Lecussan

Abstract:
Main limitations of distributed memory machines involving thousands of processors, deal with network latencies for remote data and/or programs accesses. In this paper we present multithreading techniques for parallel graph reduction model that can tolerate latencies of thousands of cycles by dynamically creating a set of threads. Efficiency is achieved by introducing fast context switch, non preemptive threads and comparative long run-lenght threads (thousand of cycles). Conventional multithreaded techniques deals with statically defined threads (at compile time) and dynamically or statically scheduling.of the work to be performed. Parallel graph reduction is an attractive model because of its simplicity and inherently distributed nature: parallelism is introduced by parallel evaluation of function parameters corresponding to dynamically created set of threads. The single assignment feature and the absence of side effect, since the internal representation of programs remains purely functional, overcomes the difficulties of synchronized accesses to shared data and scheduling of parallel activities.

Keywords: Applications



Classification:
	C.1	processor architectures
	C.2	computer-communication networks
	C.3	special-purpose and application-based systems; microprocessor/microcomputer applications; process control systems; real-time systems; signal processing systems
	C.4	performance of systems; design studies; measurement techniques; modeling techniques; performance attributes; reliability, availability, and serviceability
	D.1	programming techniques
	D.2	software engineering
	D.3	programming languages
	D.4	operating systems
	F.1	computation by abstract devices
	F.2	analysis of algorithms and problem complexity


Source:
F. Caudal, B. Lecussan, Design and Evaluation of a Multi-Threaded Architecture for Parallel Graph Reduction.
In V. Malyshkin (ed.), Parallel Computing Technologies: Proceedings of the 3th International Conference, Lect. Notes in Comp. Sci., Vol. 964, Springer, 1995, pp. 411-426

ISSN 0302-9743
ISBN 3-540-60222-4

Search LNCS articles for:
Caudal, F. ; Lecussan, B.



Scanned first page:

Designed by the Supercomputer Software Department RAS, 1998